Keynote & Invited Speakers(2020)
Dr. Doug Yu, Vice President, TSMC
Opportunities in Advanced Packaging for Heterogeneous Integration
Dr. Ravi Mahajan, Fellow, Intel
EUV Lithography – the Road to High-Volume Manufacturing
Dr. Anthony Yen, Vice President, ASML
Integrated Materials Solutions: A Path Forward For Moore's Law
Dr. Sanjay Natarajan, Vice President, Applied Materials
Partial List of other Confirmed Distinguished CSTIC 2020 Invited Speakers
Embedded ReRAM technology and neuromorphic application
Dr. Takumi Mikawa, Senior Manager, Panasonic Semiconductor Solution
Symmetric Lateral Bipolar on SOI - An Ideal Device Platform for Universal RAM
Dr. Tak H. Ning, IBM Fellow (retired)
Nanowire & Nanosheet FETs for Advanced Ultra-Scaled, High-Density Logic and Memory Applications
Dr. Anabela Veloso, Principal Member of Technical Staff, IMEC
High Yield and Superior Quality/Reliability of IGBT and Power Devices at AI Era
Dr. Minhwa Chi, SVP, SiEn (Qindao) Integrated circuits
High-Performance TFTs Based on Semiconductors and Semi-Metals
Aimin Song, Profesoor, University of Manchester
Semiconductor Quantum Dot Devices for Quantum Computing
HongWen Jiang, Professor, UCLA
Considerations of missing hole defect in EUV patterning
Hidetami Yaegashi, Chief Engineer, TEL
DuPont’s Embedded Layer Technology that Enables Advanced Lithography
Mingqi Li, Principal Research Scientist, DuPont Electronics and Imaging
  Novel Spin on Planarization Technology by Photo Curing SOC
Hikaru Tokunaga, Senior Engineer, Nissan Chemicals
Etch Proximity Correction Based on Machine Learning
Rui Chen, Associate Professor, IMECAS
Challenge of High Power LPP-EUV Source with Long Collector Mirror Lifetime for Semiconductor HVM
Hakaru Mizoguchi, Exective Vice President and CTO, Gigaphoton
Hiroshi Matsumoto, Chief Specialist, NuFlare
        Nanoimprint Performance Improvements for High Volume Semiconductor Manufacturing
Keita Sakai, General Manager, Canon
  Line Width and Roughness Measurement of Advanced FinFET Features by Reference Metrology
Masami Ikota, Senior Engineer, Hitachi High Tecnologies
Full Chip Curvilinear ILT in a Day
Leo Pang, Chief Product Officer and VP, D2S
Are Surfaces of Silicon Hardmasks Adaptive?
Dr. Xianggui Ye, Computational Materials Scientist, Brewer Science
Zhimin Zhu, Sr. Scientist, Brewer Science
Steffen Schulze, VP of Calibre Product Management, Mentor Graphics
High-NA EUV lithography enabling cost-effective shrink patterning
Jara G. Santaclara, Senior Engineer, ASML
Will Conley, Application Manager, Cymer
Advanced Lithography Material Status toward 5nm Node and beyond
Kouichi Fujiwara, General Manager, JSR(Shanghai)Co.,Ltd.
Challenges and Solutions in perpendicular STT-MRAM manufacturing
Dongchen Che, Senior Process Manager, Leuven Instruments
        Patterning of 3D Fin-Gate features at deeply scaled dimensions
Dr. Liping Zhang, R&D engineer, IMEC
Dr. Er Xuan Ping, VP of RD, ChangXin Memory Technologies
2-D Device Scaling to Nanosheet, and Technological Challenges
Dr. David Xiao, Program Manager of Core CMOS scaling, IMEC
Dr. Hua Chung, VP of RD, Mattson
        Etch Challenges and Solutions in Si Trench Etch for Power Devices
Dr. Shenjian Liu, General Manager, AMEC
Innovative Future Etch Technology by Atomic-order control
Yoshihide Kihara, Director, TOKYO ELECTRON
Dr. Ying Huang, AMAT
Dongsan Li, Naura
        Patterning challenges and perspective solutions for advanced technology nodes
Dr. Da Yang, TEL
  14nm Fin SADP Patterning Processes and Process Integration
Chunyan Yi, Principle Engineer, Shanghai IC R&D Center
The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process
Dr. Qiang Wu, Vice Director, Shanghai IC R&D Center
Fabrication and Performance Trade-offs of Future Interconnect Design and Material Options
Dr. Jonathan Reid, Fellow, Lam Research
Enabling CMOS Logic Technology Scaling beyond FinFETs
Dr. Bu Huiming, Director, IBM Research
PECVD and PEALD Low-k Silicon Carbonnitride Films for Microelectronic Applications
Prof. Jim Leu, Professor, National Chiao Tung University
Design & Technology Co-Optimization in Advanced Node
Dr. AbdelKarim Mercha, Technical Director, IMEC
Film for Advanced Patterning and Profile Control
Li Ming, Vice President, Lam Research
Evolution of FINFETS and The Role of Thin Films
Dr. Rishikesh Krishnan, Senior Technologist, IBM
BEOL Interconnect Challenges and Solutions for Advanced Technology Node
Dr. Zhu Huanfeng, Technologist, Lam Research
        Emerging Memories and their Opportunities
Tseng Chiahsun, China Technical Director, AMAT
Challenges in Dielectric Film Deposition
Xianyuan Li, Technology Director, AMAT
Mechanically Stable Ultra-low k dielectric and Air-gap technology
Dr. Mansun Chan, Chair Professor, The Hong Kong University of Science and Technology
Beyond Silicon: Low-dimensional Nanoelectronics
Dr. Shu-Jen Han, Senior Director, HFC Semiconductor Corp.
Dr. Hongbin Zhu, Sr. Director, YMTC
Exploring Aggressive BEOL Scaling Using Electrochemical ALD and ALE of Interconnect Materials
Prof. Rohan Akolkar, Professor, Case Western Reserve University
Process Innovations for Semiconductor Technology using Area Selective Atomic Layer Deposition
Prof. Stacey F. Bent, Professor, Stanford University
Dr. Bo Zheng, Sr. Principal Design Engineer, ARM
Pattern loading effect optimization of BEOL Cu CMP in 14nm technology node
Zhang Lei, Principal Engineer, HLMC
Dr. Shoutian Li, Senior Manager, Anji Microelectronics
Solving CMP challenges for chemically stable materials and 3D shapes
Dr. Hitoshi Morinaga, Senior General Manager, FUJIMI Incorporated
        In-situ end point detection and dynamic profile tuning (DPT) for CMP process
Dr. Tongqing Wang, Professor, Tsinghua University
  Modeling of chemical mechanical polishing incorporating the effect of micro contact of polishing pad
Dr. Ping Zhou, Associate Professor, Dalian University of Technology
Auto stop slurry one platen polishing application for memory devices
Dr. Jinfeng Wang, Solution engineer, Cabot Microelectronics Corporation
Optimization of Water Polishing to improve abrasive removal after CMP (Chemical Mechanical Polishing)
Dr. Taesung Kim, Professor, Sungkyunkwan University
Nano Particle Removal Using Advanced Filtration for Post CMP Clean
David Huang, VP, Pall Corporation
Prof. Ramesh Karri, Professor, New York University
Prof. Shawn Blanton, Professorr, Carnegie Mellon University
Machine and Deep Learning for Metrology of Process Control
Dr. Shay Wolfling, CTO, Nova Measuring Instrument
Dr. Tung-Yang Chen, President, AIP Technology
E-Beam Inspection challenge for new technology node and new opportunity
Dr. Wei Fang, Senior Director, ASML
  3D Heterogeneous Advanced Packaging and Manufacturing
Drink Wang, Director, TSMC
Overview of Various Approaches Toward Area Selective Deposition
Prof. Woo-Hee Kim, Assistant Professor, Hanyang University
Synthesis and applications of versatile 2-dimensional semiconductor materials
Prof. Ji Hoon Ahn, Associate Professor, Hanyang University
Surface chemistry analysis of atomic layer deposition processes
Prof. Bonggeun Shong, Assistant Professor, Hongik University
3D Heterogeneous Integration
Dr. Bill Bottoms, Chairman and CEO, 3MTS
Prof. Pol Van Dorpe, IMEC
        Spectral sensor devices for online process measurement
Ray Saupe, Researcher/Project manger, Fraunhofer ENAS
  Silicon based nanopore and its application potential
Prof. Zewen Liu, Tsinghua University
Recent Achievements and New Technologies for High Performance MEMS Sensors and Actuators
Dr.Philippe Robert, Head of the Microsystems Section, CEA-Leti France
Bin FU, Head of Marketing & Business Development, Greater China Area, Bosch Sensortec GmbH
        Monolithic integration of optical MEMS on CMOS
Matthias Schulze, Head of Engineering Department, Fraunhofer IPMS
Minimum Energy Operation of Voltage-Scaled Circuits
Prof. Hidetoshi Onodera, Professor, Kyoto University
        Monolithic 3D enabled Processing-in- SRAM Memory
Prof. Vijaykrishnan Narayanan, Distinguished Professor, Pennsylvania State University
Prof. Xin Li, Professor, Duke University
Prof. Ulf Schlichtmann, Professor, Technical University of Munich
Sign-Off Level Full Chip ESD/Reliability Design Verification In Logical Driven Layout Static Approach
Dr. Frank Feng, Director, Mentor
Prof. Hai Wang, Associate Professor, the University of Electronic Science and Technology of China
Prof. Yu-Guang Chen, Assistant Professor, National Central University
Prof. Yibo Lin, Assistant Professor, Peking University
Prof. Youngcheol Chae, Associate Professor, Yonsei University
Prof. Jose Silva-Martinez, IEEE Fellow, Texas A&M University
Confirmed Distinguished Workforce Development Speakers
Advanced Memory Technologies: MRAM
Dr. Shu-Jen Han, Senior Director, HFC Semiconductor Corp.
        Advanced Memory Technologies: RRAM
Dr. Zhiqiang Wei
Director, Rambus
  Advanced Memory Technologies: ePCM/3D-PCM
Dr. Chieh-Fang Chen
CTO, Advanced Memory Semiconductor Corp.(AMT)